Generally, a semiconductor memory device such as a dynamic random access memory (DRAM) comprises a cell array block for storing data. The cell array block includes word lines and bit lines interconnected in the form of a net and a plurality of cells connected to the bit lines and word lines.
A row decoder is adapted to select a desired one of the word lines in the cell array block. Namely, the row decoder selects one of the word lines in the cell array block corresponding to an input row address. Memory array devices, such as static random access memory (SRAM) or read-only memory (ROM) devices, require row and column address decoders to access the desired digital information of the memory array.
Memory line decoder drivers allow for driving of associated rows or columns of a memory array, on the basis of a selection signal and address signals by which the associated row or column address is coded.
In high capacity semiconductor memory devices, such as dynamic random access memories (DRAMs), which utilize a low voltage power supply, it has been necessary to utilize word line driver circuits which internally boost the power supply voltage for driving the word lines above that of the low voltage power supply. Such a word line driver circuit is depicted in FIG. 1.
With reference now to FIG. 1, the operation of the conventional word decoder driver circuit 1 will now be explained. A row decoding signal X.sub.D generated by a row decoder (not shown), is applied through an NMOS transfer transistor 2, to the gate of a pull-up NMOS transistor 3. The gate terminal of the transfer transistor 2 is connected to a power supply voltage V.sub.CC. When the row decoding signal X.sub.D is HIGH, the pull-up transistor 3 is turned ON, and pull-down NMOS transistor 4 is turned OFF by the inverted row decoding signal X.sub.D, thereby transferring the word line drive signal .phi.X.sub.1 to a word line WL of the semiconductor memory device.
In a flash memory array of the type using a non-volatile memory cell disclosed in U.S. Pat. No. 5,242,848, which is incorporated herein by reference, the control gate of the memory cell is connected to the word line, while one of the other terminals is connected to a source line. The source line is parallel to the word line in the array. Further, during programming of the cells in the memory array, the word line (control gate of the cell) must be held at a low voltage (such as 1.8V) while the source line (source of the cell) is held at a high voltage (such as 11V). During an erase operation, the word line (control gate of the cell) must be held at a high voltage (such as 12V) and the source line (source of the cell) is held at low voltage (such as 0V). Thus, a row decoder must be able to supply high voltage for erase and low voltages for fast reading.
Due to dual high and low voltage requirements, it is very difficult to optimize word line driver circuits.
Thus, it is desirable to provide a row decoder circuit that separates the high voltage operating transistors from the low voltage operating transistors to prevent or limit these occurrences.